System and Methods for Dynamic Power Estimation for a Digital Circuit

الوصف

The patented invention is a method for dynamic timing-dependent power estimation for a digital circuit containing interconnects, which result in a parasitic capacitance, and at least two gates. This method allows one to capture information on relative switching activities and timing dependence for the interconnects, to estimate the probabilities of the switching activities and each gate’s timing dependence, and to use these acquired probabilities to obtain the dynamic power estimation of the digital circuit.

النواحي

There are various parameters of interest when evaluating the performance of an integrated digital circuit. One of which is the power of consumption of an integrated digital circuit in all of its operating modes. However, accurate power estimation is a primary challenge in modern integrated circuits due to the existence of unwanted parasitic capacitances. Due to technology scaling down the sizes of transistors, currently, more than 60 percent of the dynamic power is consumed in the interconnect, or wire, capacitances. While there have been some methods to estimate the average power dissipation in digital circuits, the dynamic or switching power of the interconnect capacitances with detailed timing analysis was not before considered in previous work, as the interconnect capacitances’ values were far lower than the capacitances of the transistors.

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